(a) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a CMOS or BiCMOS semiconductor device implemented by a gate array or a standard cell.
(b) Description of the Related Art
In a CMOS or BiCMOS semiconductor device, it is usual to adopt a parasitic bipolar transistor or a parasitic MOS transistor as a protective device against an electrostatic discharge failure caused by electric charges entering from outside the semiconductor chip.
FIG. 1 is a schematic plan view of a conventional semiconductor device, showing bonding pads and protective NPN transistors protecting internal circuitry of the semiconductor device against an electrostatic discharge failure. A first, second and third signals inputted from the respective bonding pads 107, 108 and 109 are transmitted to the internal circuit (not shown) through the first, second and third signal lines 110, 111 and 112 each connected to the corresponding bonding pads 107, 108 and 109.
The signal lines 110, 111 and 112 are connected to first heavily doped N-type (N+) diffusion regions 104, 105 and 106, respectively, through respective contact holes 113. Each of the first N+ diffusion regions 104, 105 and 106 is formed within a P-well 101 disposed adjacent to the bonding pads 107, 108 and 109 and maintained at a ground potential by a heavily doped P-type (P.sup.+) diffusion region 102 and a ground line 301 connected thereto. Second N+ diffusion regions 103 maintained at a ground potential are located opposite to the respective first N+ diffusion regions 104, 105 and 106, with separating regions disposed therebetween. The separating regions are provided with a thick insulating layer or LOCOS layer 114 on the P-well 101, the thick insulating layer 114 having a minimum width determined by a current LOCOS technology.
With the construction of the semiconductor device described above, when a potential exceeding the absolute maximum rating of the semiconductor device is applied to one of the bonding pads, pad 107 for example, the protective NPN transistor, which has a collector at the first N+ diffusion region 104, a base at the grounded P-well 101 disposed below the thick insulating layer 114 and an emitter at the grounded second N+ diffusion region 103, is turned on so that the parasitic NPN transistor diverts the injected charges through the ground line 301 away from the signal line 110 and protects the internal circuit against an electrostatic discharge failure or a dielectric breakdown.
Each of the second N+ diffusion regions 103 applied at the ground potential have an enough capacity i.e., enough area for storing and discharging the electrostatic charges injected from outside the chip, thus resulting in a large area for protective devices against the electrostatic discharge failure.
Recently, miniaturization of the transistor elements of the semiconductor device has been developed markedly with the development of the fine process technology for fabricating the semiconductor device. For example, a MOS transistor having a gate of a 0.6 .mu.m length can be attained in the semiconductor device. With this fine structure of a semiconductor device, the withstand voltage of transistor elements tends to reduce together with the size of the elements. Hence, it is customary to reduce the operating voltage of the semiconductor device from 5 volt to, for example, equal to or below 3.3 volt. Some semiconductor devices, however, are still required to have a 2000 volt or more electrostatic withstand voltage.
On the other hand, the semiconductor device of a logic LSI is required to have more connecting pins, so that it is necessary, in the logic LSI, to reduce the pitch of the bonding pads and the area for protective devices correspondingly to the pitch of the bonding pads.
Under the circumstances as described above, the layout of a semiconductor device having protective devices against an electrostatic discharge failure has a problem in which, although the semiconductor device has an increasingly smaller chip size due to the development of the fine process technology, neither the area for the protective device nor the pitch of the bonding pads can be reduced because of the necessary area for storing and discharging the injected electric charges, thereby limiting the miniaturization of the chip size.